Design of A High Speed Hybrid Transistor Logic (HTL) based Cryptography

Abstract

Internet security plays crucial role in past three decades. The design of high speed Hybrid Transistor Logic (HTL) based Cryptography is implemented in this paper. So in worldwide, Advanced Encryption Standard (AES) algorithm is used. AES consists of symmetric block cipher blocks. This algorithm possess specific structure to encrypt delicate information and is connected in equipment and programming everywhere throughout the world. It is amazingly hard to programmers to get the genuine information while encoding the AES calculation. The fundamental goal of this algorithm is to build up a model that is executed for correspondence reason, and to test the created model regarding precision reason. The encryption procedure comprises the mix of different traditional methods, for example, mix columns and shift rows. Cipher text plays a major role in the data encryption block. The bits will be shifted based on the condition either even or odd.  In this AES has the advantage of being implemented in both hardware and software. Hardware implementation of the AES has lot of advantage such has increased throughput and high speed. At last the simulation results gives effective output compared to existed one.