Implementation of Low Power Cam Interface for Fault Tolerant Data Access Technique

Abstract

CAM interface is an excellent research area in VLSI technology; it has more advantage in several real-time applications such as chip-design, mobile-applications and wireless-medical applications. The fault tolerance and efficiency-related to CAM design are improved compared to previous VLSI technologies. Every VLSI chip design performance is mainly depending upon power and memory access. In this work, a new memory interface CAM model has been introducing for faster interfacing and low power applications. At final performance metrics like power, area and speed of operations are compared with existed methods. The proposed CAM interface model competes with modern technologies.