Optimized Global Routing Techniques for Efficient VLSI Physical Layout Design

Abstract

Physical Layout design is the major critical task in efficient ASIC design. According to Moore’s law sizing of integrator circuits (ICs) are becoming very compact. The trending of VLSI system design moves to System on Chip (SoC) concepts. Backend design steps like partitioning, placement, floor planning and routing are plays vital role in IC design.  Routing is the most wanted part to design optimized SoC for VLSI implementation.  There are lot of methods and techniques proposed to solve the routing problems. These methods are deals with the speed of IC routing, efficient routing and optimization of wire length. Here the study of various current algorithms in  routing to understand, how they are able to meet those challenges.

Keywords: VLSI, SoC, ASIC, Routing, Physical Layout Design and Optimized IC design.