GDI Based Ternary Prefix Networks Using CNFETS

Abstract

The paper presents the GDI based ternary prefix adder using CNFETs. Gate Diffusion Input (GDI) is the most widely used technique for reducing the power consumption. At the same time, ternary logic is introduced for reducing the logical interconnect complexity. Ternary logic is a tye of Multi-Valued Logic (MVL) in which it consists of three logics ike logic 0, logic 1 and logic 2. This GDI and ternary approaches are fused to the prefix adders. The prefix adders are most advantageous compared to the conventional complex adders. The proposed adder is implemented in the 32nm CNFET technology which has the chirality factor of (13, 0). The delay optimization is also performed in the ternary prefix adders. As a result of these fusion method, the proposed adder shown the better performance over the existing adder architectures.