An Efficient VLSI Multiplier Design For Signal Processing

Abstract

Low power VLSI design a multiplier is an extremely important factor to design a digital circuits. In general some quantifications are considered to design the low power high performance circuit that is critical path delay, circuit complexity, field size, power consumption etc., By considering these parameters to improve the effectiveness of the system energy efficient multiplier is designed and compared with other binary multiplier such as normal basis multiplier, optimum basis, reordered normal basis, Gaussian normal basis etc., the objective of this system will increase the performance of electronic circuits by the way of applying this newly designed structured multiplier into different types of filters in digital signal processing. Contributions of this field is compare and illuminate the issues of selecting appropriate multipliers for the specific application like cryptosystems, Digital signal processing etc.