Design and Implementation of I2C Master Controller for Serial Communication using VHDL
The paper focuses on the design and implementation of I2C that is inter integrated circuit master controller for single master buses. The program is written in VHDL (Very high speed hardware descriptive language) for the use in FPGA and it is simulated by using the Quartus II software. The I2C consists of simple two wire bus interface which includes a bidirectional serial data line and serial clock line that will read and write to the given user logic. The method is simple and efficient for the serial communication between the devices without any data loss. To analyze the results and the operation of I2C master controller the RTC maxim DS1307 (real time clock) as a slave device is used which is connected to the I2C bus. Using I2C bus it gets very simple to interface as many as devices to a system and to communicate to send and receive the messages or data between the devices.
Keywords: VHDL, I2C, SDA, SCL, FPGA, Master, Slave, HDL.