An Enhanced 8x8 Vedic Multıplier Design By ApplyingUrdhva-Tiryakbhyam Sutra

Abstract

Multiplication is one of the most essesntial part in arithmetic operations. It is applied in many fields such as digital signal processing, convolution, microprocessor and fourier transform etc. According to an ancient Indian vedic mathematics a rapid multiplication methodology provides as to solve problems very quickly. The vedic mathematics has an exclusive practice of calculations constructed on 16 sutras. By using this it is possible to reframe the entire mathematics.By taking this as motivation, in our proposed work, one of the best sutra has been chosen i.e. Urdhva – Triyakbhyam. It performs an optimized multiplication in terms of power and delay.This paper provides an enhanced design of 8*8 vedic multiplier which completely different from traditional method of multiplication i.e add and shift. The multiplier was designed using VHDL and implemented by Xilinx ISE series tool. From the implementation, acheived an enhanced multiplier in terms of area, delay and power.

Keywords: Multiplication, Vedic Mathematics, Vedic Multiplier, Urdhva – Triyakbhyam Sutra, VHDL.