Implementation of Efficient NOC for Unbalanced Network

Abstract

For the perfect parallel communication performance, the network on chip is a trusted structure because of the amount of processor cores are increasing in chip. In the network on chip application oriented, the traditional static router is suffered for negative performance as result is produced by using the low buffer. In this paper, application oriented network on chip dynamic router for the unbalanced Network visitors was proposed. The inter-port and intra-port buffers are combined in this router. It can be avoid the top of series blocking and making buffer methods using efficiently. Furthermore, the problem of unbalanced load properly between distinct ports on the same router can be resolved by this proposed router. Finally this application oriented network on chip is optimizing the delay and exhibits the simulation results of on-chip routers equilibrium Network visitors between ports and raise the buffer utilization by 21.8%.

 Keywords: Network on chip, Router and Buffer Allocation