FPGA implementation of 1D Median Filter architecture for de-noising application

Abstract

          In recent years, the noise reduction plays a vital role in image and signal processing application. With the help of Median Filter (MF), the noise will be removed from the input source. This work, ECG and EEG signals are consider as input source which performs the 1D median filter operation.  In this paper, Modified control module and modified rank selection with Carry Look-ahead Adder median filter (MCRM-CLA-MF) method will be introduced to improve the performance of the median filter architecture. ECG and EEG noisy signals are performing the MF architecture, which reduce the noise. From the de-noised signal, MSE and BER is evaluated.  Area, power, delay will be analysed for 5 window and 9 window for 8 bit and 16 bit median filter architecture using 180nm technology. This proposed work occupied 144 LUT, 61 flip flop, and 87 slices in Field Programmable gate Array (FPGA) Virtex 4 device. Finally, area, power, delay, Area Power Product (APP), and Area Delay Product (ADP) will be minimized in MCRM-CLA-MF method compared to conventional methods.