Analysis and Design of 6T and 8T SRAM cell using LECTOR approach

Abstract

Since from 5 decades CMOS devices are scaled down in order to achieve good performance with
respect to speed of operation, delay, power consumption, size and reliability. The primary focus is to
produce general purpose devices such as desktops, laptops, palmtops, printers and communication
devices such as fax machine, cell phones etc., in more compact form in terms of size, speed, delay and
power dissipation, for this reason we are migrating to new technology. The memory unit in these
devices are built using SRAM or DRAM cell for storage purpose. Through this paper we are
exploring alternate methods of designing SRAM cell. So that memories become more compact and
faster. All the alternate designs are simulated using Microwind in 90nm process technology with
BSIM4 MOS transistor models of level 54.