MULTI-PORTED MEMORY ON FPGA FOR A HIGH PERFORMANCE FIR FILTERS

Abstract

In present days FPGA (Field Programmable Gate Arrays), multi-ported recollections are utilized for the most part. FPGAs give an appealing stage to construct multi-ported memory. BRAMs (Block RAMs) are for the most part utilized for multi-ported memory plans on FPGA. This paper initially presents 2R1W memory as 2R1W/4R memory; consequently 4R1W requires less BRAMs than 2R1W memory structure. Contrasted and the Hierarchical Bank Division with XOR (HBDX) and Bank Division with remap table (BDRT) and applies 2R1W/4R modules as building obstructs, the proposed procedure incorporates HBDX and BDRT and applies as 8R2W;hence 8R2W requires fewer BRAMs than 4R1W. The proposed design is used for the efficient storage of memory and to increase the capacity of memory. For complex multi-ported memory design, this approach can achieve higher clock frequencies. The combination of HBDX and BDRT for 8R2W technique is applied in the memory unit of FIR (Finite-impulse Response) filter, where the coefficient storage unit of the FIR filter needs a memory to store the impulse responses. Hence it can be used for the efficient storage of impulse responses