LOW POWER FLIP-FLOP DESIGN USING DOUBLE EDGE TRIGGERING TECHNIQUE

Abstract

In a ultralow-power genuine single-stage timing flip-flop (FF) plan accomplished utilizing just 19 transistors is existing work. It beats the 16 transistor in Flip lemon. The plan follows a Flip Flop rationale structure and highlights a cross breed rationale configuration including both static-CMOS rationale and reciprocal pass-transistor rationale. In the plan, a rationale structure decrease plot is utilized to diminish the quantity of transistors for accomplishing high force and defer execution. In spite of its circuit straightforwardness, no inside hubs are left skimming during the activity to keep away from spillage power utilization. Right now, planned utilizing Double Edge Triggered Technique. This force decreasing method is applied to advance the structure.